Effects of gate stack engineering and thermal treatment on electrical and interfacial properties of Ti/Pt/HfO2/InAs metal insulator\r\nsemiconductor (MIS) capacitors were systematically evaluated in terms of transmission electron microscopy, energy dispersive\r\nX-ray spectroscopy, current-voltage, and capacitance-voltage characterizations. A 10 nm thick Pt metal effectively suppresses the\r\nformation of interfacial oxide, TiO2, between the Ti gate and HfO2 gate dielectric layer, enhancing the gate modulation on the\r\nsurface potential of InAs. An in situ HfO2 deposition onto the n-InAs channel with an interfacial layer (IL) of one-monolayer InP\r\nfollowed by a 300?C post-metal-anneal produces a high-quality HfO2/InAs interface and thus unravels the annoying Fermi-level\r\npinning, which is evidenced by the distinct capacitance dips in the high-/low-frequency C-V characteristics. The interface trap\r\nstates could be further suppressed by replacing the InP IL by an As-rich InAs, which is substantiated by a gate leakage reduction\r\nand a steep voltage-dependent depletion capacitance.
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